1. Field of Invention
This application relates generally to test and measurement equipment and more specifically to interfaces between testers and devices under test.
2. Discussion of Related Art
Automated test equipment is used extensively to ensure the proper functioning of semiconductor devices. Testing allows for the removal of defective devices from fabrication lots, thus eliminating further unnecessary processing and packaging. In addition, test results may be used to identify malfunctioning fabrication equipment requiring maintenance, thereby increasing device yields. Test results also allow for binning of devices possessing varying performance and operating specifications resulting from processing variations. For example, a device with test results indicating the device does not meet desired specifications may be packaged and sold at a lower price with labeling indicating reduced operating ranges and/or performance.
To measure device operation, automatic test equipment (also referred to as a tester) applies input signals to a device under test (“DUT”) and detects the resulting DUT output signals. FIG. 1 illustrates, in simplified form, a tester 100 comprising a controller 120 and multiple channels 1301, 1302, . . . 130N that, for each cycle, generate signals for or measure signals from specific points on the device under test. Controller 120 may include a computer that is programmed to direct the testing process, process data collected during tests and interface with an operator. Controller 120 may also include circuitry shared by multiple channels or circuitry unrelated to the channels.
In the example of FIG. 1, channel 1301 is shown in additional detail. Channel 1301 includes circuitry comprising a pattern generator 140, a timing generator 150, and pin electronics 160. The pattern generator 140 is programmed with a “pattern” that defines the operation of the channel during each cycle. For example, pattern generator 140 may indicate the channel should drive a signal with a particular value to DUT 110.
Timing generator 150 creates timing signals that control signal transitions, such as by defining the start of a time when a value should be driven or the time at which the value on a line should be measured.
The pin electronics 160 includes circuitry that drives a stimulus signal into line 1801, which will ultimately be fed into DUT 110. Drive circuitry includes a driver 162. In the simplified block diagram of FIG. 1, driver 162 is shown to be preceded by flip-flop 164. Flip-flop 164 is clocked by the timing signal from the timing generator 150 and supplied with data from the pattern generator 140. Flip flop 160 illustrates that both the value output by driver 162 and the time it is output can be controlled.
Pin electronics 160 may also detect signals on line 180, via comparator 166. Comparator 166 receives an input on line 1801 from DUT 110 and a reference input from a programmable reference value generator 168. The output from comparator 166 is applied to the input of a latch 165. Latch 165 is clocked by the timing generator 150, which dictates the output value of comparator 166 that is passed along to the pattern generator 140 for further processing. Pin electronics 160, via comparator 166 and the reference value generator 168, indicate whether the detected signal from line 1801 is larger or smaller than a specified value indicated by the programmable reference generator 168.
Pin electronics 160 are shown in simplified form. Driver 162 may, for example, receive multiple control signals to specify when a signal is to be provided and its level. Driver 162 might also include a control input to “tri-state” the driver at certain times so that it does not drive line 180. For example, driver 162 may be “tri-stated” when comparator 166 is reading a signal on line 180. Such an example is suited for digital signal detection, but in other implementations, such as analog signal detection, the tester may be adapted to perform other operations. However, FIG. 1 is sufficient to illustrate that a test point on DUT 110 may be connected to a channel in a tester that is loaded with both a comparator and a driver.
Signals exchanged between tester 100 and DUT 110 pass through interface 189. In the simplified sketch of FIG. 1, interface 189 includes a device interface board (“DIB”) 190, a connector 172 and a probe card 174. Interface 189 also includes mechanical support and alignment structures, but such structures are not shown for simplicity.
Interface 189 is connected to tester 100 through lines 1801, 1802, . . . 180N. These lines are connected to DIB 190. Lines 1801, 1802, . . . 180N may include spring pins that contact pads on DIB 190 or other types of connectors to make a separable connection between DIB 190 and tester 100.
DIB 190 is a circuit board containing traces or other signal paths to route the test and response signals to and from the DUT. DIB 190 may be fabricated using conventional printed circuit board techniques and may include electronic components that customize DIB 190 for testing a specific style of DUT.
DIB 190 is connected through connector 172 to probe card 174. Connector 172 may be a “pogo tower” or similar structure holding numerous spring pins that make a connection between DIB 190 and probe card 174. Alternative connectors include “interposers.”
Probe card 174 may also use a printed circuit board as a substrate. Probe card 174 includes compliant members 1701, 1702, . . . , 170N that serve as probes to contact test points on DUT 110. Examples of such compliant members are microscopic contact probes sold by Formfactor Corporation of Livermore, Calif., or those described in U.S. Pat. Nos. 5,900,738; 6,043,563; 6,049,976; and 6,184,053 B1.
Some semiconductor DUTs source enough current to drive a response signal through the DIB and any loads (e.g., 50 Ohm driver loads) present in the tester channel so that the signal can be reliably measured at comparator 166. However, we have recognized that low-power devices may only be able to drive loads with 10 pF or less of capacitance and negligible resistance. The inability to drive the load presented by the tester is compounded for devices outputting high frequency signals. In these situations, a conventional tester interface will not suffice.
A need therefore exists for an improved interface between a tester and a device under test, particularly for testing devices that operate on low-power/high-frequency signals.